A semiconductor integrated circuit (IC) typically includes electrically isolated elements, such as a transistor formed at a substrate, a contact hole, and an interconnection selectively connecting the otherwise isolated elements. For example, the contact hole and the interconnection may connect a first active region to a second active region, a first gate electrode to a second gate electrode and/or a gate electrode to active region as needed.
FIG. 1A is a cross-sectional view illustrating a conventional interconnection structure. In FIG. 1A, the region A illustrates an interconnection between active regions, the region B illustrates an interconnection between gate electrodes, and the region C illustrates an interconnection of a gate electrode to an active area. Referring to FIG. 1A, in the region A, a field region 6 is disposed in the substrate 2 to define a first active region 16a and a second active region 16b that are doped with impurities. An interlayer dielectric 20 is provided on the substrate 2. Contact plugs 22 that electrically connect to the active regions 16a and 16b are formed through the interlayer dielectric 20. An interconnection line 34 is provided on the interlayer dielectric 20 to electrically connect the contact plugs 22 to each other. Thus, the first active region 16a is connected to the second active region 16b through the contact plugs 22 and the interconnection line 34.
In the region B of FIG. 1A, an active region 16c doped with impurities is provided in the substrate 2 between field areas 6. A first conductive line 10a and a second conductive line 10b are disposed at respective ones of the field areas 6. While the conductive lines 10a and 10b are formed at the field areas 6 in FIG. 1A, the conductive lines 10a and/or 10b may become a gate electrode when crossing over the active region 16c. An interlayer dielectric 20 is provided on the substrate 2 including the conductive lines 10a and 10b. Contact plugs 24 are connected to the conductive lines 10a and 10b through the interlayer dielectric 20. The contact plugs 24 are also connected to each other through the interconnection line 36. Thus, the contact plugs 24 and the interconnection line 36 electrically connect the first conductive line 10a to the second connective line 10b. 
The region C of FIG. 1A illustrates a MOS-transistor having a gate structure and a source/drain region 18 on both sides of the gate structure. The gate structure includes a gate insulator 8, a gate electrode 10c, and spacers 14 on sidewalls of the gate electrode 10c. The source/drain region 18 is provided by a lightly doped region 12 and a heavily doped region 16d. An interlayer dielectric 20 is provided on the substrate 2 having the MOS-transistor. And a contact plug 26 is also formed to electrically connect both the gate electrode 10c of the MOS-transistor and a doped active region 16d through the interlayer dielectric 20. The contact plug 26 is connected to an interconnection line 38.
As mentioned above, conventionally, otherwise electrically isolated regions are electrically connected to each other using contact plugs, such as the contact plugs 22, 24 and 26 and interconnection lines, such as the interconnection lines 34, 36 and 38. The interlayer dielectric 20 is selectively etched to form a contact hole where the contact plugs 22, 24 and 26 will be disposed. Processes for forming a hole pattern to provide contact plugs may become difficult as a semiconductor devices become more highly integrated.
In addition, as the semiconductor device becomes more highly integrated, processes for isolating adjacent patterns may become more difficult. For example, when a misalignment arises in a photolithography process for forming a contact hole on conductive lines 10a and 10b of the region B, an electrical short may occur between the active region 16c doped with impurities and the conductive lines 10a and/or 10b. To overcome this problem, the conductive lines 10a and 10b have been used as an ion implantation mask to provide self-alignment of the active region 16c. Thus, the active region 16c of the region B disposed between the field areas 6 is not doped with impurities if the conductive lines cross the region between the field areas 6. Such a case is illustrated in FIG. 1B. Where the conductive line 10 covers the region between the field areas 6, an unwanted MOS-transistor may be formed that may degrade the performance of the device.